module bus_addr_gen
#(
  parameter DFT_POINTS = 8
)(
  //OUTPUTS
  output [clogb2(DFT_POINTS) - 1:0] addr_bus,    //Address to bus operations
  //INPUTS
  input enable,                                  //Enables the next address generation
  input clear,                                   //Clear the address when started the core
  input order,                                   //Select direct or bit reversed order: 1 -> direct, 0-> bit reversed
  input clk,                                     //Clock
  input rst_n                                    //Reset, active low, asyncrhonous
);
`include "fft_functions.v"
localparam DFT_BITS = clogb2(DFT_POINTS);

reg  [DFT_BITS - 1:0] addr_gen;
wire [DFT_BITS - 1:0] addr_reversed;

always @(posedge clk, negedge rst_n)
  begin
    if(!rst_n)
      addr_gen <= {DFT_BITS{1'b0}};
    else
      if(clear)
        addr_gen <= {DFT_BITS{1'b0}};
      else
        if(enable)
          addr_gen <= addr_gen + 1;
  end

generate
  genvar i;
  for(i = 0 ; i < DFT_BITS; i = i + 1)
    begin
      assign addr_reversed[i] = addr_gen[DFT_BITS - 1 - i];
    end
endgenerate

assign addr_bus = (order) ? addr_gen : addr_reversed; 
endmodule
